1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to a transistor device with improved source/drain junction architecture and various methods of making such a device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that substantially determines performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped channel region disposed between the highly doped source/drain regions. Device designers are under constant pressure to improve the electrical performance characteristics of semiconductor devices, such as transistors, and the overall performance capabilities of integrated circuit devices that incorporate such devices.
Ion implantation is a technique that is employed in many technical fields to implant dopant ions into a substrate so as to alter the characteristics of the substrate or of a specified portion thereof. For example, the rapid development of advanced devices in the semiconductor industry is based on, among other things, the ability to generate highly complex dopant profiles within tiny regions of a semiconducting substrate by performing advanced implantation techniques through a masking. In implanting specified ions into a substrate, the desired lateral implant profile may be readily obtained by providing correspondingly adapted implantation masks. A desired vertical implant profile may be achieved by, among other things, controlling the acceleration energy of the ions during the implantation process such that the majority of the ions are positioned at a desired depth in the substrate. Moreover, by appropriately selecting the dopant dose, i.e., the number of ions per unit area of the ion beam impinging on a substrate, comparably high concentrations of atoms may be incorporated into a substrate as compared to other doping techniques, such as diffusion. In the case of an illustrative transistor, ion implantation may be used to form various doped regions, such as halo implant regions, extension implant regions and deep source/drain implant regions, etc.
An illustrative ion implantation sequence employed in forming an illustrative transistor 30 will now be discussed with reference to FIGS. 1A-1D. FIG. 1A depicts the transistor 30 at an early stage of fabrication, wherein a gate structure 14 has been formed above a semiconductor substrate 10 in an active region that is defined by a shallow trench isolation structure 12. The gate structure 14 typically includes a gate insulation layer 14A and a conductive gate electrode 14B. As shown in FIG. 1A, an implantation mask 17 is formed above the substrate so as to expose the transistor. The ion implantation mask 17 is typically a patterned layer of photoresist material and it may be formed using traditional photolithography tools and techniques. In one illustrative embodiment, a plurality of angled ion implantation processes are performed to form the schematically depicted so-called halo implant regions 15 in the substrate 10. The halo implant regions 15 are typically formed by performing a series of two or four angled implant processes, during which the substrate 10 is rotated 180° or 90° after each of the angled implantation processes is performed. The halo implant regions 15 are doped with the same type of dopant material as is the active region of the substrate 10. For example, for an NMOS device, the halo implant regions 15 may be P-doped regions so as to reinforce the dopants in the P-doped active region. In the case of a PMOS device, the halo implant regions 15 would be N-doped regions. The dopant concentration of the halo implant regions 15 may vary depending upon the particular application. The implant angle used in forming the halo implant regions 15 may also vary depending upon the particular application. Among other things, the purpose of the halo implant regions 15 is to reduce so-called short channel effects on minimum channel length devices, i.e., the proximity from the left and the right halo implant regions will help to avoid premature punch-through and keep the threshold voltage of the transistor device high enough for proper functionality.
As indicated in FIG. 1B, after the halo implant regions 15 are formed, a so-called extension ion implantation process is typically performed to form so-called extension implant regions 16 in the substrate 10. The extension implant process is typically performed through the same masking layer 17 that was used when forming the halo implant regions 15. In the case of an NMOS device, the extension implant regions will be N-doped regions. The concentration of dopant materials in the extension implant regions 16 may vary depending upon the particular application. In some embodiments, the extension implant regions 16 may be self-aligned relative to the sidewalls of the gate structure 14. In other applications, a small sidewall spacer (not shown) may be formed adjacent to the gate structure 14 prior to forming the extension implant regions 16. The extension implant regions 16 typically have a lower dopant concentration and a shallower depth than that of so-called deep source/drain implant regions that, as discussed more fully below, will be formed in the substrate 10.
FIG. 1C depicts the device 30 after several process operations have been performed. First, the patterned implant mask 17 used when performing the process operations described above in connection with FIGS. 1A-1B is removed. Then, one or more sidewall spacers 18 are formed proximate the gate structure 14. The spacers 18 may be formed by depositing a layer of spacer material and thereafter performing an anisotropic etching process. Next, a so-called source/drain doping process is performed on the transistor 30 by means of an epitaxy and/or ion implantation process to form so-called deep source/drain implant regions 20 in the substrate 10. As noted above, the source/drain ion implantation process is typically performed using a higher dopant dose and at a higher implant energy than the ion implantation process that was performed to form the extension implant regions 16. The halo implant regions 15 have a sufficient concentration of counter-dopant materials so as to effectively overwhelm the dopants implanted during the source/drain implantation process. As a result, the source/drain implant regions 20 effectively stop on the halo implant regions 15.
Thereafter, as shown in FIG. 1D, a heating or anneal process is performed to form the final source/drain regions 22 for the transistor 30. This heating process repairs the damage to the lattice structure of the substrate material as a result of the implantation processes and it activates the implanted dopant materials, i.e., the implanted dopant materials are incorporated into the silicon lattice. As depicted, the halo regions 15 limit the depth of the final source/drain regions 22. As device dimensions are continually being reduced, it is very important that the depth of the source/drain regions 22 for a transistor be very shallow, e.g., approximately 15 nm or less in current-day technologies, and that the implanted dopants are, to the extent possible, fully activated. Thus, heating processes such as a flash anneal or a laser anneal are performed for a very short duration, e.g., 1250° C. for a duration of 2-10 milliseconds, and are performed to limit the diffusion of the implanted ions, so as to maintain the desired shallow dopant profile, while at the same time trying to maximize dopant activation. In general, the higher the annealing temperature, the greater the extent of dopant activation. For previous device generations, a typical anneal process might be a rapid thermal anneal process performed at a temperature of about 1080° C. for a much longer duration of about 1-2 seconds. However, the very short millisecond anneal times performed to activate very shallow source/drain regions are insufficient to cure all of the damages to the substrate resulting from the ion implantation processes. After a flash or laser anneal process is performed, the source/drain regions 22 of the transistor 30 will have an amorphous region (where there is a sufficient concentration of ions to enable the region to conduct current) and a semi-amorphous region (where implanted ions are not of sufficient concentration or not activated). The depth of the amorphous regions may be approximately 3-7 nm and 40-50 nm, for the extension implant regions 16 and the deep source/drain implant regions 20, respectively, of the source/drain region 22 of the transistor 30. As a result, the depth of the semi-amorphous region would tend to overlap with the PN junction in the source/drain region of the device, which may result in higher leakage currents, which tend to reduce the electrical performance of the resulting device and an integrated circuit device incorporating such transistors.
The present disclosure is directed to a transistor device with improved source/drain architecture and various methods of making such a device that may solve or reduce one or more of the problems identified above.